1. Field of the Invention
The present invention relates to a method for forming CMOS devices and, more particularly, to a cost effective method for forming low-voltage CMOS transistors with a thin layer of gate oxide, and high-voltage CMOS transistors with a thick layer of gate oxide.
2. Description of the Related Art
Current-generation 0.25-micron MOS transistors are an example of the continuing miniaturization of MOS transistors which have fallen in size from the micron range to the low submicron range in a few short years.
The advantages of utilizing ever smaller MOS transistors are that these devices reduce the cost of providing logic functions due to the increased number of transistors that can be integrated into a single package, and extend the life of battery-operated devices due to the lower voltage requirements of the smaller transistors.
One problem with utilizing current-generation 0.25-micron transistors, however, is that these transistors often function poorly when required to provide analog and mixed-signal functions due to the higher leakage currents and smaller dynamic ranges of these transistors.
With digital transistors, higher leakage currents contribute to increased power dissipation whereas leakage currents in analog transistors are particularly problematic in that these currents may render some analog circuits completely non-functional or lead to random errors. The higher leakage currents in deep sub-micron processes is attributed to non-complete turn-off of the transistors due to the low threshold voltages. This is particularly true for very short channel transistors.
With respect to the dynamic range, current-generation 0.25 micron devices typically operate off of a 2.5-volt supply voltage, whereas previous generation 0.35 and 0.5 micron devices commonly operated off of 3.3 and 5-volt supply voltages, respectively. Thus, current-generation MOS transistors provide approximately two-thirds to one-half of the dynamic range of the older devices.
One solution to this problem is to utilize the 0.25-micron transistors when implementing the digital functions of a circuit, and the 0.35 or 0.5-micron transistors when implementing the analog or mixed-signal functions of the circuit.
However, when 0.25-micron transistors and 0.35 or 0.5-micron devices are utilized in the same circuit, the layer of gate oxide used with the 0.35 or 0.5-micron transistors must be thicker than the layer of gate oxide used with the 0.25-micron transistors due to the higher voltages that are applied to these transistors. Without the thicker layer of gate oxide, the higher voltages, e.g., 3.3 or 5 volts, would prematurely degrade the gate oxide layer of the 0.35 or 0.5-micron transistors.
For example, the thickness of the gate oxide layer used with a 0.25-micron CMOS process is approximately 55 .ANG., while the thickness of the gate oxide layer used with 0.35 and 0.5-micron CMOS processes ranges from approximately 70 .ANG. to 120 .ANG..
Thus, to form 0.25-micron transistor types and 0.35 or 0.5-micron transistor types on the same chip requires a process flow which is capable of forming multiple thicknesses of gate oxide. Current processes, however, typically require several additional masking steps to achieve different thicknesses of gate oxide.
Thus, there is a need for a process that forms 2.5-volt CMOS transistors with a thin layer of gate oxide, and 3.3 or 5-volt transistors with a thick layer of gate oxide.